Double Patterning for Memory ICs

In order to continue technology shrink roadmaps and to provide year by year smaller chips with more functionality, nearly all of the leading edge semiconductor companies have adopted double patterning process technologies in their fabrication lines to bridge the time until next generation EUV lithography reaches production maturity. Double patterning technology can be classified into two major main streams, however its implementation and especially the details of the process integration vary strongly among the semiconductor company and every manufacturer found his own optimum. Therefore the given schemata will focus on the key principles. We will not stress material combinations, but point out particular challenges, show some detailed analyses, and sketch solutions.